The present invention relates to a semiconductor device and a manufacturing method for the semiconductor device and is favorably utilized in, for example, a power semiconductor device and a manufacturing method for the power semiconductor device.
In the field of vertical-type power MOSFETs, that is, the power semiconductor devices, adoption of a super junction structure is now being examined in order to suppress on-resistance while maintaining a breakdown voltage.
For example, in Japanese Unexamined Patent Application Publication No, 2007-335844, there is disclosed a semiconductor device which has adopted the super junction structure in a cell region and a peripheral region. Then, semiconductor pillar regions having the super junction structure are formed such that the closer to the termination of each of the cell and intermediate regions the semiconductor pillar region is located, the more the depth thereof is reduced stepwise.